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What’s New in Xilinx ISE Design Suite 13.1
What's New in CORE Generator and IP
The following describes what's new in CORE Generator? software and IP cores:
Introducing CORE Generator IP with Virtex?-7 and Kintex?-7 support
New IP Cores
?
Audio, Video and Image Processing IP
?
Object Segmentation v1.0 (AXI4-Lite)
-
Used in conjunction with the Image Characterization LogiCORE IP to convert
statistical data provided into a list of objects that meet a user-defined set of
object characteristics.
?
AXI Video Direct Memory Access v1.0 (AXI4, AXI4-Stream, AXI4-Lite)
-
Provides a flexible interface for controlling and synchronizing video frame
stores from external memory. Multiple VDMAs from different clock domains
can be linked together to control frame store reads and writes from multiple
sources.
?
Communication DSP Building Blocks
?
Linear Algebra Toolkit v1.0 (AXI4-Stream)
-
-
Implements basic Matrix operations - Matrix-Matrix Addition, Subtraction,
Matrix-Scalar Multiplication and Matrix-Matrix Multiplication.
This IP provides flexible and optimized building blocks for developing
complex composite functions for various signal and data processing
applications.
?
FPGA Features and Support
?
7 Series FPGA Transceivers Wizard v1.3
-
-
Configures one or more Virtex-7 and Kintex-7 FPGA GTX transceivers either
from scratch, or using industry standard templates, using a custom Verilog or
VHDL wrapper.
Also provides an example design, testbench, and scripts to allow you to
observe the transceivers operating in simulation and in hardware.
?
XADC Wizard v1.2
-
The XADC Wizard generates an HDL wrapper to configure a single 7 Series
FPGA XADC primitive for user-specified channels and alarms.
?
Standard Bus Interfaces and I/O
?
7-Series Integrated Block for PCI Express (PCIe) v1.0 (AXI4-Stream)
-
-
Implements 1-lane, 2-lane, 4-lane, or 8-lane configurations. The IP uses the 7
Series Integrated Hard IP Block for PCI Express in conjunction with flexible
architectural features to implement a PCI Express Base Specification v2.1
compliant PCI Express Endpoint or Root Port.
Unique features of the LogiCORE IP for PCI Express are the high
performance AXI Interface, optimal buffering for high bandwidth
applications, and BAR checking and filtering.
?
Wireless IP
?
Triple Rate SDI v1.0 (AXI4-Stream)
-
Provides receiver and transmitter interfaces for the SMPTE SD-SDI, HD-SDI,
and 3G-SDI standards.
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.1)
www.xilinx.com
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相关PDF资料
EF-EDK-FL SOFTWARE EDK EMBED FLOAT
EF-ISE-DSP-FL SOFTWARE ISE DSP EDITION
EF-ISE-SYSTEM-FL ISE DESIGN SYST FLOATING LICENSE
EF-VIVADO-HLS-FL VIVADO HLS, FLOATING LICENSE
EFM32-GXXX-PTB BOARD PROTOTYPING FOR EFM32
EFS315 FUSE INDUST 315A 415V BS IEC
EHBNCSCB CONN EH BNC T/H SOLDER CUP BLK
EHE004 BOARD ENERGY HARVESTING
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EFDSS645B25A 制造商:Panasonic Industrial Company 功能描述:DELAY LINE
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EFE01A 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM)
EFE01A-F 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM)
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EFE01B 制造商:CRYDOM 制造商全称:Crydom Inc., 功能描述:Power Modules